Compilers use overlays, which are typically added at an origin of a cell that is being customized in order to personalize a circuit layout. When a given circuit has several orthogonal customization possibilities, there will need to be one or more overlays for each of those options. When using several overlays for each of the orthogonal customization possibilities, the complexity is increased. For example, when decoding each address input, typically two to four overlays may be required.
In a high level circuit design, netlists can be in the form of a hardware description language such as verilog or a circuit level description such as a simulation program with integrated circuit emphasis (“spice”) or circuit design language (“cdl”). However, existing compilers require specific knowledge from the compiler code, such as a lower-level level layout in order to generate graphical data of a given circuit.